Ansys Q3D: Simulation of Parasitic Effects in Power Electronics
Learn how to use Ansys-Q3D-Extractor-based 3D circuit design to localize and optimize interference effects This training is offered as a 2-day course.
Duration
2 days
Prerequisites
None
Software used
Ansys Q3D
- Determining parasitic induction, resistance load per unit length, and capacitance
- Familiarization with physics-related issues, software operation & effective workflows
- Generating behavior models for the purposes of circuit simulation
- Parametric simulation and optimization
Description
The evaluation and improvement of power electronics assemblies in terms of their parasitic inductance is, from both a technical and an economic perspective, of paramount importance. The loop inductance of the commutation circuit has a big impact on the switching characteristics of power semiconductors. The line inductance of intermediate circuit capacitors limits the PWM switching frequency and the potential currency signals. The gate-actuation-related coupling inductance at conductive paths may lead to switching characterized by oscillation and instability. When it comes to components connected in parallel, differences in DC and AC line impedance lead to uneven loads on such components.
Ansys 3D Extractor represents the industry standard when it comes to determining parasitic inductance, resistance load per unit length, and capacitance arising from the 3D geometry of assemblies such as packages, busbars, and PCBs. Practice-oriented examples are employed during the training to provide you with everything you need when it comes to using Ansys Q3D Extractor effectively; this covers operation of the software, physical and numerical modeling, and effective workflows. This training is ideal for development engineers and hardware developers seeking to evaluate and optimize the effects of parasitic properties even during the initial phases of power electronics circuit design.
Detailed agenda for this 2-day training
Day 1
01 Hands-on: getting going with Q3D Extractor
- The concept of the simulation environment
- Exercise: the influence of bonding wire arrangement on the inductance of a power semiconductor package
- Introduction to the Ansys Electronics user interface
- Importing and generating geometry plus how to allocate materials
- Parameterization
- Allocating electric meshes and terminals
- Simulation settings
02 Calculating capacitance
- Evaluation of results: frequency-dependent capacitance and conductance
- Portraying field results
- Parametric studies
- Exercise: extracting the capacitance of a power semiconductor
03 Calculating inductance
- Evaluation of results: frequency-dependent parasitic inductance and resistance load per unit length
- Portraying field results
- Parametric studies
- Using Q3D solver technology to extract AC and DC inductance
- Determining frequency-dependent impedance
- Exercise: calculating the inductance of AC busbars
04 Linking to circuit simulation
- The significance of partial inductance when it comes to circuit simulation
- Linking to circuit simulation within a range of frequencies
- The behavior of passive components
- Exercise: parallel-switched capacitors within intermediate circuits – extracting input impedance and current distribution
Day 2
05 Extracting parasites when working on PCBs
- Importing layouts and preparing simulation models
- Important variables when characterizing a DC-DC transformer
- The relationship between these output quantities and the response of circuits and EMC
- Exercise: a DC-DC transformer
06 Characterizing components when simulating circuits
- The description of inductive and capacitive components
- Testing models of semiconductors
- Overview of the device characterization tool in Simplorer
- Exercise: circuit simulation for a DC-DC transformer
07 Simulation of transient switch signals
- Dynamic link to Ansys Simplorer
- Ways of improving circuit simulation convergence
- Exercise: DC-DC transformer switching characteristics
08 Discussion and a preview of additional topics
- Calculating wire-based emissions
- Thermal coupling
- Scripting
- Optimization
Your Trainers
Frank Weiand
Placement in the CADFEM Learning Pathway
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