Evaluate Signal and Power Integrity of PCB Designs with SIwave
Understand and improve circuit board layouts using field simulation
In this training you will learn how to use simulation to accelerate and optimize the development process of PCBs. This training is offered as a 2-day course.
Duration
2 days
Prerequisites
None
Software used
Ansys SIwave
- Avoid rework through extended design rule checks
- Enhance development processes through greater understanding of design
- Identify and improve critical points
- Perfect for beginners: No simulation knowledge necessary
Description
As a result of progressive miniaturization, greater integration density and higher switching speeds, the printed circuit board itself has become a complex component as a carrier for circuit components. To achieve a ‘First Time Right’ development process, the use of simulation is essential for designers and layout engineers. Only with simulation electromagnetic field effects can be considered for all aspects of signal transmission.
This training course provides technical know-how on signal and power supply integrity simulation in Ansys SIwave. You will deepen your acquired knowledge via numerous practical examples (e.g. Computer on Module – COM). In the course you will be taught to identify, analyze and optimize critical points in PCB designs. To meet design requirements (e.g. EMC requirements and industry standards), you will check the virtual prototype of the PCB by simulations and evaluate different variants in all phases of the design process. This procedure allows you to significantly reduce development times.
The training is aimed at hardware developers and PCB designers for all types of electronics who want to identify optimized design variants in the early design phase or need to provide well-founded predictions on the behavior of their layouts.
Detailed agenda for this 2-day training
Day 1
01 Analyzing and optimizing DC Power GND concepts
- Hands-On-Start: DC power supply integrity of a Computer on Module (COM)
- Voltage drop during the supply of active components
- Power sharing for VIAs
- Analyze and evaluate current densities
- Evaluation of losses
02 Analyzing and Optimizing AC Power GND Concepts
- Supply impedance and resonances in the power/GND system
- Target impedance and low impedance power supply design
- Influencing factors: Layer structure, decoupling capacitors and their connection
- Workshop: AC supply integrity of the Computer on Module
03 Sanity Check: Hands-On Start into Signal Integrity (SI)
- Workshop: Plausibility check using Impedance Scan and Crosstalk Scan analyses
- Signals on electrically long networks
- Impedances of transmission lines
04 Design, Analyze and Optimize Signal Paths
- Workshop: Channel Analysis of the Computer on Module
- Characterization of transmission lines using S-parameters
- Find defects - TDR profile (Time Domain Reflectometry) as fingerprint of the transmission path
- Single-ended and differential signals
- Influence of Pad Entries, VIAs and reference planes
Day 2
05 Investigation of Transient Signals
- Workshop: Study of a DDR3 bus
- Signal crosstalk
- Transition from frequency domain to time domain
- Calculation of eye diagrams and bathtub curve for evaluation of transmission paths
06 Consideration of Driver Models
- Consideration of driver models for the exact description of transient signal characteristics
- Workshop: Continuation of the investigation of the DDR3 bus
- Integration of IBIS models (Input/Output Buffer Information Specification) with the help of SIwizard
- Comparison of methods without driver model using the Channel Operating Margin (COM)
07 Introduction to EMC Analysis at the PCB Level
- Supply network as unwanted antenna
- Workshop Radiated Emissions: Investigation of the far and near field of the DDR3 bus
- Understanding the coupling path using AC voltage and current distributions
08 Outlook on Further Topics
- Determination of parasitic effects on PCB with the CPA solver
- Model export to Ansys HFSS
- Parametric Simulation with SIwave in the Ansys Electronics Desktop
Your Trainers
Steffen Seewald
Frank Weiand
Andrey Gettikh
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For more information on the validity and how booking with the code ACADEMIC50 works, please visit our page on training for academic users.
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If the minimum number of attendees is not reached, we reserve the right to cancel the training seven days before it is due to start at the latest. We are happy to inform you on changing your booking to an alternative date. Please note that we accept no liability for hotel or travel bookings that attendees have already made.
Usually the training courses start at 9:00 am and end at 5:00 pm of the respective local time. The actual course times will be stated in the booking confirmation. Please note that, depending on the training host, there may be a possible time shift between your and the provider's local time. Therefore all local times are provided with the valid time shift to Greenwich Mean Time (GMT).